1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a multi-bit and multi-level non-volatile memory device and methods of operating and fabricating the same.
2. Description of the Related Art
A non-volatile memory device, for example, a flash memory device, includes a conductive floating gate between a control gate and a semiconductor substrate. The floating gate is used as a storage node for storing electric charge. The flash memory operates by forming a conductive channel, i.e. a current flow, in a semiconductor substrate using induced change in threshold voltage which in turn corresponds to electric charge stored in the floating gate.
Meanwhile, a Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) based memory device, another type of non-volatile memory device, includes a trap-type storage node positioned between a control gate and a semiconductor substrate. The operation of the SONOS memory is similar to that of the flash memory.
Because of limitations of micro-pattern processing technologies for manufacturing non-volatile memory devices, however, increase in the capacity and operation speed memory devices reach design limits. Accordingly, alternative approaches for increasing the capacity and operation speed of memory device are the focus of ongoing research.
An example of one approach is a structure having two-sidewall floating gates formed on both sidewalls of a word line select transistor disclosed in U.S. Pat. No. 6,133,098 by Seiki Ogura et al. entitled “PROCESS FOR MAKING AND PROGRAMMING AND OPERATING A DUAL-BIT MULTI-LEVEL BALLISTIC FLASH MEMORY”, incorporated herein by reference. The dual-sidewall floating gates, formed adjacent to a word line, share a bit line and a source, and do not require an element isolating region, thereby increasing device integration. In addition, a multi-level program operation, which has a plurality of threshold voltage levels by controlling a bit line voltage, can be performed. However, the flash memory disclosed by Seiki Ogura et. al has drawbacks in that the operations of the two-sidewall floating gates are limited to 2-bit mode and the reduction in the width of a word line select gate is limited to suppress the short channel effect.
An example of another approach is a multiple-bit non-volatile memory using a non-conductive trapping gate disclosed in U.S. Pat. No. 6,670,669 by Shoichi Kawamura et al. entitled “MULTIPLE-BIT NON-VOLATILE MEMORY UTILIZING NON-CONDUCTIVE CHARGE TRAPPING GATE”, incorporated herein by reference. The non-volatile memory device disclosed by Shoichi Kawamura et al. can perform multi-bit operations by locally storing electric charge in several places of a non-conductive trapping gate. However, the non-volatile memory device disclosed by Shoichi Kawamura et al. cannot effectively suppress the short channel effect because of the use of a planar-type transistor structure, and thus, cannot readily reduce the length of the control gates. Thus, the device of Shoichi Kawamura et al. is likewise limited in its ability to increase the integration of a memory device.